1. Field of the Invention
The present invention relates to a spread spectrum clock (SSC) generator, and more particularly, to a spread spectrum clock generator having a delayer.
2. Description of the Related Art
In a computer system, in order to improve system performance, it is possible that a central processing unit is operated at a higher clock frequency to increase a processing speed. However, the higher clock frequency makes the computer system and its peripheral devices (e.g., a memory card, a graphic card, etc.) be operated at a higher frequency and generate an amount of EMI (electromagnetic interference). Herein, the higher the clock frequency is increased, the more EMI is generated from the computer system and its peripheral devices. Therefore, to reduce the EMI, there have been proposed various techniques using shielding, filtering, etc., but it costs a great deal to follow and comply with EMI regulations, so that a method to fundamentally suppress the EMI is needed.
As the method to fundamentally suppress the EMI, there is a spread spectrum technique that modulates the clock frequency, thereby spreading over a wider range of bandwidth its energy concentrated on a narrow frequency band. Most of conventional spread spectrum clock generators are realized by using a PLL (phase locked loop) circuit. The PLL circuit receives an input signal and generates a clock signal having a desired frequency.
However, in the conventional spread spectrum clock generator using the PLL circuit, an attenuation degree of the EMI decreased according to an increment of the system clock frequency. Thus, the realization of the PLL circuit in the spread spectrum clock generators is very difficult at the higher clock frequency.
Accordingly, there has proposed a spread spectrum clock generator having a delayer, which has more effective suppression of the EMI.
As shown in FIG. 11, the conventional spread spectrum clock generator having the delayer includes a delay chain 110 including a plurality of AND gates 112, 114, 116 . . . , a selector 126 selecting one of channels inside the delay chain 110, and a multiplexer 134 including a plurality of AND gates 136 and a plurality of OR gates 138.
The delay chain 110 includes the AND gates 112, 114, 116 . . . connected in series, and therefore a propagation delay of each AND gate 112, 114, 116, . . . accumulates. Here, the respective AND gates are different from each other in the propagation delay, so that a total delay is determined according to the channels from an input terminal 118 of the AND gate 112, 114, 116 . . . to an output terminal 128. For example, no propagation delay is caused in a first channel 120, the propagation delay is caused in a second channel 122 by one AND gate 112, and another propagation delay is caused in a third channel 124 by two AND gates 112 and 114. At this time, a plurality of signals respectively entered through the AND gates 112, 114, 116, . . . are synthesized into a single signal, so that the AND gates 112, 114, 116 . . . are used as the delayer.
The selector 126 outputs one of selection signals 130 according to a predetermined pattern every time a clock signal 132 is inputted, thereby selecting one of the channels inside the delay chain 110.
The multiplexer 134 transmits a specific signal, which is outputted from the respective AND gates 112, 114, 116 . . . employed as the delayer 110 in response to the one of the selection signals 130 of the selector 126, to the output terminal 128. Here, the channels from the input terminal of the respective AND gates 112, 114, 116 . . . of the delay chain 110 to the output terminal 128 have the same distance, so that the total delay is determined according to what channel inside the delay chain 110 is selected.
With this configuration, in the conventional spread spectrum clock generator, the selector 126 outputs one of the selection signals 130 every time the clock signal 132 is inputted through the input terminal 118. Then, one of the AND gates 136 inside the multiplexer 134 is selected in response to the one of the selection signals 130 of the selector 126. Then, the clock signal 132 is transmitted from the delay chain 110 to the selected AND gate 136, and then transmitted to the output terminal 128 via the OR gates 138. At this time, during one period of the clock signal 132, other AND gates 136 are not operated except for the selected AND gate 136. Thereafter, at the following period of the clock signal, the selector 126 outputs another selection signal 130, and repeats the above process. As described above, the selector 126 is synchronized with the clock signal 132, that is, outputs one selection signal 130 in response to every clock signal, so that the output terminal 128 outputs a phase-modulated clock signal based on the original clock signal. Thus, the spread spectrum clock is realized.
In short, in the conventional spread spectrum clock generator using the delayer, the spread spectrum clock is realized by controlling the number of logic gates to be included in the channel. However, the conventional spread spectrum clock generator using the delayer cannot minutely control the total delay below an inherent propagation delay due to one logic gate. Generally, the propagation delay due to one inverter is 70˜80 ps (picosecond), and the propagation delay due to one NAND gate is about 100 ps. Consequently, the conventional spread spectrum clock generator using the delayer cannot control the propagation delay of several tens or below ps. Further, the conventional spread spectrum clock generator using the delayer must include the selector and the multiplexer, thereby increasing a production cost.